There have been ongoing developments in the microfabrication of semiconductor devices. Along with this, the resolution of LSI has been improving according to the scaling law. Microfabrication of semiconductor devices involves not just smaller element size, but the size of an element isolation region for isolating elements is reduced as well.
As a technique of element isolation, a method known as LOCOS (Local Oxidation of Silicon) has been commonly used. In the LOCOS method, a thermal oxidation film (field oxidation film) is formed only in the element isolation region, by taking advantage of the oxidation-tolerant property of a silicon nitride film.
However, the LOCOS method has a problem known as the “bird's beak.” The “bird's beak” is a phenomenon in which the field oxidation film spreads to areas to be element regions. Where there is a bird's beak, the actual dimensions of element regions are smaller than the designed dimensions. A bird's beak can effectively be suppressed by reducing the amount of field oxidation. However, this is set against reduced element isolating power. Microfabrication of semiconductor elements has come to the level where it is now difficult to suppress bird's peak while at the same time sustain element isolating power. That is, the LOCOS method has almost seen its limit.
A recent alternative to the LOCOS method is an element isolation method known as STI (Shallow Trench Isolation), intended to suppress bird's beak. Briefly, the STI method forms a trench (groove) by etching a surface of a semiconductor substrate. This is followed by formation of an isolation film (insulating layer) in the trench. The isolation film is then planarized to achieve element isolation. An advantage of this method is that it provides a good element isolating power by allowing the size (depth) of the trench to be increased along a direction perpendicular to the substrate surface. The method also suppresses the lateral spread of the isolation film. As a result, a semiconductor device is realized that has good element isolating power and allows for microfabrication. That is, by the element isolation employing the STI method, fabrication of semiconductor devices with an improved level of integration is possible.
In the STI method, a silicon oxide film is commonly used as the isolation film embedded in the trench. In order to improve density of the silicon oxide film, the silicon oxide film is subjected to a heat treatment after embedding it in the trench. However, owning to the fact that the silicon oxide film and the semiconductor substrate are made of different materials, the heat treatment causes a compressive load to be applied on the channel region of the semiconductor substrate. This generates a compressive stress in the channel region. The compressive stress strains the Si lattices in the channel region. This decreases electron mobility. As a result, the drain current of MOSFET is reduced. The influence of compressive stress becomes prominent as the size of element-forming region is reduced by the microfabrication of elements.
A solution to the problem of compressive stress is described in Japanese Laid-Open Patent Publication No. 2004-207564 (published on Jul. 22, 2004, corresponding US Patent Publication US2004/0126990 A1). This publication teaches canceling the compressive stress of the silicon oxide film by the tensile stress of the silicon nitride film formed in the trench, as shown in FIGS. 5(a) through 5(h).
With reference to FIGS. 5(a) through 5(h), the following will describe a conventional semiconductor device and a fabrication method. FIGS. 5(a) through 5(h) are cross sectional views illustrating fabrication steps of the semiconductor device. FIG. 5(h) is also a cross section representing a structure of the conventional semiconductor device.
First, as shown in FIG. 5(a), a silicon oxide film 111 and a silicon nitride film 112 are deposited on a surface of the silicon substrate 110. The silicon nitride film 112 is then coated with a resist film (not shown), and an element-isolating pattern 113 is formed by exposure and development. The element-isolating resist pattern 113 is formed on an element-forming region (active region), and an opening defines an element isolation region.
Then, as shown in FIG. 5(b), the silicon nitride film 112, the silicon oxide film 111, and the semiconductor substrate 110 are successively etched to form an element-isolating trench 126, using the resist pattern 113 as a mask.
Thereafter, the resist pattern 113 is removed. As shown in FIG. 5(c), the surface of the silicon substrate exposed in the trench is subjected to thermal oxidation to form a silicon oxide film 114. Then, a silicon nitride film 115 is formed to cover the silicon oxide films 114 and 111, and the silicon nitride film 112.
Next, as shown in FIG. 5(d), a silicon oxide film 116 is formed to completely fill the trench 126.
Then, as shown in FIG. 5(e), surface irregularities on the silicon oxide film 116 are improved by chemical machine polishing, without exposing the silicon nitride film 115. The silicon oxide film 116 is then etched back.
Next, as shown in FIG. 5(f), the exposed portion of the silicon nitride film 115 is removed by a phosphoric acid (H3PO4) boil.
Next, as shown in FIG. 5(g), a silicon oxide film 117 formed by a chemical vapor deposition (CVD) method is deposited on the entire surface on the film-bearing side of the semiconductor substrate 110, so as to fill the trench 126. This is followed by planarization etching by chemical machine polishing, which exposes the surface of the silicon nitride film 112 in the element-forming region.
Thereafter, as shown in FIG. 5(h), the silicon nitride film 112 is removed by a phosphoric acid (H3PO4) boil, followed by removal of the silicon oxide film 111 with hydrofluoric acid. Next, well implantation is performed to form a well region 118 and a well region 119. This is followed by formation of a gate oxidizing film 120 and a gate electrode 21. Then, by source and drain implantation, a source region and a drain region 122 are formed.
In the conventional technique, the compressive load applied on the channel-forming region of the element-forming region is reduced by the tensile stress of the silicon nitride film 115. This increases the electron mobility in the N-channel MOSFET among the MOSFETs adjoining the trench 126, as compared with the case where the silicon nitride film 115 is not provided.
In the P-channel MOSFET, however, reducing the compressive load decreases the hole mobility as compared with the case where the silicon nitride film 116 is not provided. This reduces the drain current. The reduced drain current in the MOSFET slows the response speed of the MOSFET.